1. Field of the Invention
The present invention relates generally to methods for forming aperture fill layers within apertures within substrates employed within microelectronic fabrications. More particularly, the present invention relates to methods for forming planarized aperture fill layers within apertures within substrates employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become common in the art of microelectronic fabrication, and in particular within the art of semiconductor integrated circuit microelectronic fabrication, to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronic fabrications trench isolation regions which are nominally co-planar with adjoining active regions of the semiconductor substrate within which are formed the trench isolation regions. Trench isolation regions which are nominally co-planar with adjoining active regions of a semiconductor substrate are desirable within the art of semiconductor integrated circuit microelectronic fabrication, since such trench isolation regions when nominally co-planar with adjoining active regions of a semiconductor substrate most favorably accommodate an attenuated depth of focus of a photoexposure apparatus typically employed in defining patterned microelectronic layers upon the semiconductor substrate having the nominally co-planar isolation regions and active regions formed therein.
Of the methods for forming trench isolation regions nominally co-planar with adjoining active regions of a semiconductor substrate within which are formed those trench isolation regions, high density plasma chemical vapor deposition (HDP-CVD) methods when employed in conjunction with planarizing methods, such as but not limited to chemical mechanical polish (CMP) planarizing methods, are presently of particular interest. High density plasma chemical vapor deposition (HDP-CVD) methods are understood in the art as plasma enhanced chemical vapor deposition (PECVD) methods undertaken simultaneously with bias sputtering methods, where a deposition rate within a plasma enhanced chemical vapor deposition (PECVD) method employed within a high density plasma chemical vapor deposition (HDP-CVD) method is greater than a sputtering rate within a bias sputtering method employed within the high density plasma chemical vapor deposition (HDP-CVD) method. High density plasma chemical vapor deposition (HDP-CVD) methods are presently of considerable interest in conjunction with planarizing methods for forming trench isolation regions within isolation trenches within semiconductor substrates since high density plasma chemical vapor deposition (HDP-CVD) methods typically provide superior gap filling properties when forming a blanket trench fill dielectric layer upon a semiconductor substrate and within an isolation trench within the semiconductor substrate, from which blanket trench fill dielectric layer upon planarizing is formed a trench isolation region within the isolation trench within the semiconductor substrate.
While trench isolation regions formed employing high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with planarizing methods, and in particular chemical mechanical polish (CMP) planarizing methods, are thus desirable within the art of microelectronic fabrication for forming isolation regions nominally co-planar with adjoining active regions of a semiconductor substrate, high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction, in particular, with chemical mechanical polish (CMP) planarizing methods are nonetheless not entirely without problems within the art of semiconductor integrated circuit microelectronic fabrication for forming trench isolation regions nominally co-planar with adjoining active regions of a semiconductor substrate within which are formed those trench isolation regions. In that regard, trench isolation regions formed from blanket trench fill dielectric layers formed employing high density plasma chemical vapor deposition (HDP-CVD) methods, since such blanket trench fill dielectric layers are typically formed with uniquely irregular surface profiles, are often difficult to effectively planarize, such as chemical mechanical polish (CMP) planarize, to form chemical mechanical polish (CMP) planarized high density plasma chemical vapor deposited (HDP-CVD) trench isolation regions with uniform planarity of the trench isolation region and minimal residue formation over portions of the semiconductor substrate adjacent the trench isolation region.
It is thus towards the goal of forming within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronic fabrications planarized high density plasma chemical vapor deposited (HDP-CVD) trench isolation regions with uniform planarity and minimal residue formation that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards providing methods for forming within apertures within topographic substrates employed within microelectronic fabrications plannarized high density plasma chemical vapor deposited (HDP-CVD) aperture fill layers with enhanced planarity and minimal residue formation.
Various methods have been disclosed within the art of microelectronic fabrication for forming microelectronic layers with desirable properties within microelectronic fabrications.
For example, Liu, in ULSI Technology, C. Y. Chang & S. M. Sze, eds., McGraw-Hill, 1997, pp. 422-23, discloses, in general, characteristics of high density plasma chemical vapor deposition (HDP-CVD) methods for forming silicon oxide layers within semiconductor integrated circuit microelectronic fabrications.
In addition, Sato, in U.S. Pat. No. 5,182,221, discloses a bias electron cyclotron resonance high density plasma chemical vapor deposition (ECR-HDP-CVD) method for forming within an aperture within a substrate layer employed within a microelectronic fabrication an aperture fill material without increase in aspect ratio of the aperture and without void formation within the aperture fill material formed within the aperture. The electron cyclotron resonance high density plasma chemical vapor deposition (ECR-HDP-CVD) method realizes the foregoing objects by employing within the electron cyclotron resonance high density plasma chemical vapor deposition (ECR-HDP-CVD) method a vertical:horizontal deposition rate ratio equal to two times a depth of the aperture divided by a width of the aperture.
Further, Sato et al., in U.S. Pat. No. 5,242,853, discloses an additional electron cyclotron resonance high density plasma chemical vapor deposition (ECR-HDP-CVD) method for forming within a trench within a substrate employed within a microelectronic fabrication a patterned planarized trench fill dielectric layer while effectively removing portions of the trench fill dielectric layer residues formed upon portions of the substrate adjoining the trench. The method employs a lateral directional etch method to remove portions of a blanket electron cyclotron resonance high density plasma chemical vapor deposited (ECR-HDP-CVD) dielectric layer formed upon edges of the substrate adjoining the trench, prior to masking portions of the electron cyclotron resonance high density plasma chemical vapor deposited (ECR-HDP-CVD) dielectric layer formed within the trench and subsequently etching the trench fill dielectric layer residues formed upon portions of the substrate adjoining the trench.
Still further, Jain, in U.S. Pat. No. 5,494,854, discloses a method for forming, with enhanced manufacturing throughput, enhanced gap filling characteristics and enhanced planarity, a planarized inter-level dielectric (ILD) layer formed interposed in-part between the patterns of a patterned conductor layer within a semiconductor integrated circuit microelectronic fabrication. The method employs when forming the planarized inter-level dielectric (ILD) layer a bilayer inter-level dielectric (ILD) layer comprising: (1) a planarizing first dielectric layer formed at least in part interposed between the patterns of the patterned conductor layer, the planarizing first dielectric layer being formed employing a high density plasma chemical vapor deposition (HDP-CVD) method, the planarizing first dielectric layer in turn having formed thereupon; (2) a conformal dielectric polish layer which polishes at a rate greater than the planarizing first dielectric layer. The bilayer inter-level dielectric layer is then polished employing a chemical mechanical polish (CMP) planarizing method to form a planarized bi-layer inter-level dielectric (ILD) layer with the above noted desirable properties.
Finally, Jain et al., in U.S. Pat. No. 5,686,356, discloses a method for forming, with enhanced planarity, a planarized inter-level dielectric (ILD) layer planarizing a patterned conductor layer within a microelectronic fabrication. The method employs a reticulated patterned conductor layer of dimensions such that the planarized inter-level dielectric (ILD) layer when formed upon the reticulated patterned conductor layer is formed with enhanced planarity.
Desirable in the art of microelectronic fabrication are additional high density plasma chemical vapor deposition (HDP-CVD) methods and materials, which in conjunction with planarizing methods and materials may be employed to form within apertures within topographic substrate layers employed within microelectronic fabrications planarized aperture fill layers with enhanced planarity and attenuated residue formation. More particularly desirable in the art of microelectronic fabrication are additional high density plasma chemical vapor deposition (HDP-CVD) methods, which in conjunction with planarizing methods may be employed to form within isolation trenches within semiconductor substrates trench isolation regions with enhanced planarity and attenuated residue formation.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.